1. Technical Field
This invention relates generally to testing of semiconductor devices, and more particularly, to a method of testing read-only memory (ROM) using automatic test pattern generation (ATPG) patterns.
2. Background Art
FIG. 1 illustrates a read-only memory (ROM) 22 including a decoder 24 and an array 25 in the form of an embedded block in an overall semiconductor integrated circuit device 26. As an example, six address lines (generally indicated at 28) are included in order to provide a plurality of addresses to the decoder 24. The number of addresses is given by 26=64 different addresses, corresponding to 64 locations 301-3064 in the ROM 22. The ROM locations 301, 302, 303, . . . 3064 include respective data set 30A1-30A64, each four bits wide, with the number of variations being given by 24=16 possible different data sets (it will be understood that some locations in the ROM 22 include identical data sets). The ROM 22 includes four data output lines (generally indicated at 34), for providing from the ROM 22 the four-bit-wide data set from an addressed ROM location. The ROM 22 has connected thereto surrounding logic, generally indicated at 36, 37 for operative association with the ROM 22, and other parts (not shown) of the integrated circuit device 26.
In testing the structure of FIG. 1, and with reference to FIG. 2, it is well known to provide an ATPG-compliant model of the structure of FIG. 1 (Step 1), based on elements including the ROM 22 and surrounding logic 36, 37. An automatic test pattern generation tool (for example the Mentor Graphics, Inc. FastScan) is then applied to this model (Step 2) to generate an ATPG test pattern (Step 3) which is then applied to the hardware of FIG. 1 (Step 4). The ATPG tool generates the test pattern primarily based on the surrounding logic 36, 37 of the model and, depending on the form of the decoder 24, may or may not generate all 64 possible addresses to the ROM 22. In the situation where all 64 addresses are not generated, clearly not all locations in the ROM 22 are addressed, and tests for the locations will not be generated by the ATPG tool. Even if the form of the decoder 24 is such that the ATPG tool will generate all 64 addresses, the ATPG tool will generate a test for a location only if an output from that location is provided both in the case where a high logic level (logic level 1) is provided to that location, and in the case where a low logic level (logic level 0) is provided to that location. However, a conventionally designed ROM will generate an output from a location only with the input to that location logic level 1, and an output from that location will not be provided if the input to that location is logic level 0. In such case, the ATPG tool will not generate a test for that location. Hence, full coverage in testing the ROM 22 is not provided.
Therefore, what is needed is a method for providing that an ATPG tool, in generating a test pattern, is forced to generate a test for each location in a ROM, so that when such test pattern is applied to hardware including the ROM, the test pattern provides exhaustive testing of the ROM.